• 2 years ago
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DIGITAL SYSTEM DESIGN-UEC612

46:09
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Lecture 1 Binary codes | DIGITAL SYSTEM DESIGN-UEC612
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24:37
Lecture 2 Error Detecting Codes | DIGITAL SYSTEM DESIGN-UEC612
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40:38
Lecture 3 Hamming Code | DIGITAL SYSTEM DESIGN-UEC612
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47:14
Lecture 4 | 4-variable and 5-variable Karnaugh Maps | DIGITAL SYSTEM DESIGN-UEC612
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46:05
Lecture 5 | 6 variable K Maps | DIGITAL SYSTEM DESIGN-UEC612
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56:26
Lecture 6 QM Method | DIGITAL SYSTEM DESIGN-UEC612
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51:02
Lecture 7 | QM Method continues | DIGITAL SYSTEM DESIGN-UEC612
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47:21
Lecture 8 VEM Method | DIGITAL SYSTEM DESIGN-UEC612
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49:59
Lecture 9 Combinational Circuits L9 | DIGITAL SYSTEM DESIGN-UEC612
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30:51
Lecture 10 Carry Look Ahead Adder L10 | DIGITAL SYSTEM DESIGN-UEC612
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33:16
Lecture 11 BCD Adder and Magnitude Comparator L11 | DIGITAL SYSTEM DESIGN-UEC612
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47:35
Lecture 12 Decoders and Encoders L12 | DIGITAL SYSTEM DESIGN-UEC612
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50:03
Lecture 13 Multiplexer and De-multiplexer L13 | DIGITAL SYSTEM DESIGN-UEC612
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16:54
Lecture 14 PLDs-ROM | DIGITAL SYSTEM DESIGN-UEC612
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18:19
Lecture 15 PLA L15 | DIGITAL SYSTEM DESIGN-UEC612
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28:41
Lecture 16 PAL L16 | DIGITAL SYSTEM DESIGN-UEC612
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30:05
Lecture 17 Code Converters L17 | DIGITAL SYSTEM DESIGN-UEC612
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35:45
Lecture 18 Sequential Cicuits-NOR and NAND Latch,,L18 | DIGITAL SYSTEM DESIGN-UEC612
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33:14
Lecture 19 Flip Flops L19 | DIGITAL SYSTEM DESIGN-UEC612
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32:32
Lecture 20 Characterstic Table and Flip flop Conversion L20 | DIGITAL SYSTEM DESIGN-UEC612
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32:15
Lecture 30 Analysis of Clocked Sequential Circuits L30 | DIGITAL SYSTEM DESIGN-UEC612
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41:52
VHDL1_Sept09_20 | DIGITAL SYSTEM DESIGN-UEC612
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43:27
VHDL2_Sept11_20 | DIGITAL SYSTEM DESIGN-UEC612
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43:22
VHDL3_Sept14_20_T
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38:15
L31 State Reduction and Assignment
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40:34
L28 Design of Synchronous Counters
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12:42
L27 Shift Register Counters
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28:11
L26 Synchronous Counters
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36:43
L22 Shift Registers
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26:21
L25 Asynchronos Counters (Continued...)
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23:05
L23 Universal Shift Registers
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29:43
L29 Design of Synchronous Counters(Contd..)
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33:53
L24 Asynchronous Counters
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